Projects

| Risc V

Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules required including the Hazard detection unit, Forwarding Unit, Branch Prediction, and the Five pipeline stages are simulated and verified the functional testing with test benches on ModelSim.
| Pipeline_simulator

RISCV The integer pipeline simulator includes a forwarding unit, a hazard detection unit with the static branch prediction technique predict not taken. 8-stage pipeline with a 2-stage fetch unit and 3-stage memory unit. branch is computed in the EX stage and forwarding from memory is done through MEM2 stage.

| Nivas

Implementation of 1st order Software PLL for Grid Tie Micro Inverter on Micrium RTOS (µC/OS-II) to schedule tasks such as ADC Read Task, PLL Task, SPWM Generation Task using Round Robin Scheduler on TIVA-C (TM4C123GH6PM).

| Rt_dvfs_simulator

Simulation and Comparison Real-Time DVFS scheduling algorithms. Implemented the RT-DVFS scheduling algorithms static voltage scaling and the cycle conserving. Both the techniques were EDF based scheduling and were implemented in python. Compared and evaluated both the scheduling techniques on energy consumption for different test cases

| Habitist

Modified and updated github action that integrates native habit tracking in todoist. Apply Seinfield's "Don't Break the Chain" method for habit building (Made by amitness).